Trace the feedback connection
- Select CLK1 and U1. Find the clock-to-CLK wire and the inverted /Q-to-D feedback wire.
- The example uses a 100 Hz clock. Choose Digital logic in Analysis and a 0.1 s duration, then press Run.
Check your result
The logic analyzer displays clock, /Q and Q traces.
Compare clock and output periods
- Open Logic analyzer if it is not already selected. Match each colored trace to its terminal labels.
- Q changes state on rising clock edges. Compare two clock periods with one Q period.
Check your result
The clock period is about 10 ms; the Q period is about 20 ms (50 Hz). Q and /Q are complementary after initialization.
If you get stuck: These are ideal Boolean models, without propagation delay, voltage thresholds or metastability behavior.
Repeat at another clock frequency
- Select CLK1, change Frequency to 200 Hz, and run again.
- Export all measurements as CSV if you want the sampled logic states.
Check your result
Q now repeats at about 100 Hz. The CSV contains digital states versus time.